XILUME interface controller ICsEngineering catalog
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XILUME CONTROLLER ICs

Standard interface functions in one XILUME controller.

Select an orderable signal configuration, use its fixed functional pinout, and integrate the controller with the released reference design.

Use controller selector Compare models

PRODUCT PRINCIPLE

One XILUME model defines one complete behavior.

Each controller is supplied as a defined XILUME product. Customers design around its documented electrical characteristics, fixed pinout, and supported interface behavior.

FIXED

Interface function

Communication handling, buffering, status logic, and host protocol are defined by the selected XILUME model.

FIXED

Functional pinout

Every orderable model has a controlled pin definition for power, host, field interfaces, and status signals.

SELECTABLE

Operating settings

Supported bus speeds and normal operating options are selected through the documented host protocol.

EXTERNAL

Physical-layer design

Transceivers, isolation, termination, connectors, and protection follow the reference schematic and system needs.

ENGINEERING MODEL FAMILY

Current USB-hosted configurations.

Part numbers and values remain engineering specifications until the corresponding release-controlled datasheet is published.

MODELHOSTFIELD INTERFACESMEMORY CLASSPACKAGE CLASSSTATUS
XIC-U2C2R2USB 2.0 FS2 CAN FD + 2 RS-485256 KB64 pinEngineering
XIC-U2C2USB 2.0 FS2 × CAN / CAN FD128 KB48 pinEngineering
XIC-U2R2USB 2.0 FS2 × RS-485128 KB48 pinEngineering
XIC-USMB1USB 2.0 FSSmart Battery / SMBus128 KB48 pinEngineering

The released product datasheet, not this comparison table, controls final electrical, memory, package, and environmental specifications.

RELEASE-CONTROLLED FILE SET

Design information follows the exact controller model.

Files are grouped by orderable part number and product revision so customers can verify that the schematic, software, and device behavior belong together.

01Datasheet

Electrical limits, package dimensions, operating conditions, and functional description.

PDF
02Pinout table

Pin number, name, direction, voltage domain, reset state, and required connection.

PDF / CSV
03Reference schematic

Minimum controller circuit plus recommended transceiver, USB, and protection design.

PDF
04Host protocol

Command frames, responses, error codes, timeouts, and supported configuration settings.

PDF
05Software package

Windows and Linux test tools, examples, device identification, and verification procedure.

ZIP
06Revision record

Product revision, validation state, known limitations, and controlled change history.

PDF

CONTROLLER ROADMAP

Additional host interfaces will use the same selection system.

SPI, UART, and I²C-hosted parts remain visible in the selector as roadmap functions. They will receive orderable models only after electrical definition, device validation, and documentation are complete.

SPI-hosted controllersPlanned
UART-hosted controllersPlanned
I²C / SMBus-hosted controllersPlanned
Additional channel combinationsPlanned