Device documents
| Topic | XL1326 · V1.05 | XL1326-A · V1.00 |
|---|---|---|
| Complete datasheet | 28 page PDF | 25 page PDF |
| Pin configuration | §3 · p8 ↗ | §3 · p6 ↗ |
| Host interface and protocol | §6 · p13 ↗ | §6 · p10 ↗ |
| Power and clock | §7 · p20 ↗ | §7 · p18 ↗ |
| Package drawing | §10 · p26 ↗ | §10 · p23 ↗ |
Reference circuits
The reference circuits cover device power, clock, reset, USB and transceiver logic connections. Each link opens the corresponding page in the original datasheet.
XL1326
Dual CAN FD and six USART channels
Open reference circuit · p24 ↗§9.5 · PDFXL1326-A
Dual CAN FD
Open reference circuit · p22 ↗For XL1326 RS-232, RS-422 and RS-485 transceiver connections, see §9.6 · p25
IC pins are logic-level interfaces. CANH/CANL and RS-232/RS-485 field wiring connect through the appropriate external transceivers. Isolation, power, protection and connectors are part of the system design.
Host interfaces
| Device | Windows | Linux | Download |
|---|---|---|---|
| XL1326 | 8 COM ports: 2 CAN FD protocol endpoints + 6 serial ports | 2 × SocketCAN + 6 × TTY | Driver package → |
| XL1326-A | 2 CAN FD protocol COM endpoints | 2 × SocketCAN | Driver package → |
Choose the separate driver package matching the device marking. Windows COM numbers and Linux CAN interface names are assigned dynamically.
CAN FD COM endpoints use the Xilume CAN command protocol. See Section 6 of the corresponding datasheet for channel mapping, message framing and commands.
Protocol capabilities
The current protocol supports Classical CAN and CAN FD data frames with BRS. RTR remote frames are not represented; extended frames with numeric IDs at or below 0x7FF cannot be distinguished from standard frames, and ESI is not encoded in the receive format. Channels share the USB Full-Speed link; validate aggregate throughput under the intended workload.
Design review
- Check the device and pin orientation
Use the corresponding top-view pin diagram, then check power connections, reserved-pin bias and NC-pin handling.
- Check the clock and transceivers
Both datasheets specify an 8.000 MHz main clock. Select external transceivers for each channel’s voltage and data-rate requirements.
- Review layout and assembly
Check USB differential routing, decoupling and reference planes against the datasheet. Package drawings define geometry; confirm PCB land patterns and stencil dimensions with the assembly process.
- Validate the complete system
Exercise concurrent channels, USB reconnection, host reboot and power recovery, then validate temperature, interference and termination for the application.